1. Field of the Invention
This invention relates to a low latency, high bandwidth bus system for use in a high-performance, large capacity memory system, logic system or combined logic and memory system, and particularly to such a bus system suitable for conventional VLSI devices or wafer-scale integration devices with a circuit module-oriented architecture.
2. Description of the Prior Art
Many traditional bus systems use reduced-swing signal transmission (i.e., a signal swing smaller than the supply voltage), including TTL standard, to enable high speed operations. Problems usually arise in data transmission when either of the following conditions exists: (i) the rise or fall time of the transmitted signal is a significant fraction of the clock period; (ii) there are reflections on the signal bus which interfere with the rising or falling transitions of the signal. The data transfer rate is limited in part by whether signal integrity is compromised as a result of the above conditions. The other hindrance is the maximum cycle rate of the memory and controller. To increase data bandwidth, the above conditions should be avoided.
High frequency data transmission through a bus requires a high rate of electrical charge (Q) transfer on and off the bus to achieve adequate rise and fall times. To avoid condition (i) above, large transistors in the memory and controller are needed to source and sink large amounts of current required to switch the signal levels. This requirement undesirably causes increased silicon area, bus capacitance, power consumption and power supply noise.
Assuming transmission rate is a constant, there are several known ways to improve the situation. One is to minimize the bus capacitance, but this severely constrains the bus length as well as the number of devices that can be attached to the bus. The second method is to reduce the voltage swing needed to distinguish between logical 1 and 0. This reduces the amount of charge transfer; thereby, power consumption, noise and silicon area can be reduced. To minimize condition (ii), impedance matching using proper line termination can be used to reduce reflection. The reference voltage, or trip point, of a signal bus is the voltage level which delineates a logical 1 from a logical 0. Most digital CMOS circuits use supply voltage Vdd/2 as the trip point, and this permits the circuits to operate with symmetric noise margins with respect to the power and ground supply voltages. This also results in symmetrical inverter output rise and fall times because the PMOS and NMOS transistors in the circuit have equal strengths due to the fact that Vdd/2 is the trip point. With the exception of center-tap termination (CTT), prior art small swing (&lt;1.5 v peak-to-peak) I/O schemes generally have symmetric voltage swings about a reference voltage that has no intended relation to the "natural" implicit reference voltage (Vdd/2) about which typical digital CMOS circuit operates. Examples of these schemes are the Gunning-Transceiver Logic (GTL) (R. Foss et al, IEEE Spectrum Oct. 1992, p. 54-57, "Fast Interfaces for DRAMs"), Rambus DRAM (M. Farmwald et al, IEEE Spectrum Oct. 1992, p. 50-51 "A Fast Path to One Memory"; and R. Comeford et al, "Memory Catches Up", p. 34-35, same issue). These require an explicit voltage reference source, either internal or external to the chip. In order to attain the desired attributes of symmetric noise margins and rise and fall time, these schemes must translate their small swing I/O reference point to the "natural" reference. This translation incurs the penalty of additional circuit delay and complexity. Furthermore, each bus line is terminated to the reference supply through a resistor with a value matching bus line impedance.
Center-tap termination, (R. Foss et al, IEEE Spectrum Oct. 1992, p. 54-57, "Fast interfaces for DRAMs") differs in that this scheme can accommodate Vdd/2 as the I/O reference without the need for an external reference supply voltage. Bus line resistive termination to Vdd/2 can be attained through a resistive voltage divider coupled between Vdd and ground. Small swing signal is attained through a feedback mechanism which reduces the drive of the output driver once the output voltage crosses the termination reference voltage (Vdd/2).
There are several drawbacks to this scheme. First, the logic required to perform the feedback mechanism is directly in the data path. This means added data-out delay or latency. Also the transistor count and static DC power required to implement this feedback control logic, which includes a threshold detector, may become a burden. Finally, this scheme requires two termination resistors per bus line. If a relatively wide bus were to be employed, this results in high component count and increase in required board space.